1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) circuit, a semiconductor integrated circuit, an electronic device, and a control method of a phase-locked loop circuit, and particularly to an improvement in control response in a phase-locked loop circuit.
2. Description of the Related Art
A phase-locked loop circuit (that may be referred to also as a phase-locked circuit) may be incorporated into an electronic device.
An ordinary phase-locked loop circuit generates an internal clock signal of a desired oscillation frequency in synchronism with an external reference clock signal. Specifically, the phases and frequencies of the external reference clock signal and an internally generated comparison clock signal are compared with each other by a phase and frequency comparator. A phase-difference signal corresponding to a result of the comparison is supplied to a loop filter section to extract a low-frequency component of the phase-difference signal and set the low-frequency component as an oscillation control signal. The oscillation control signal output from the loop filter section is supplied to an oscillator (a voltage controlled oscillator or a current controlled oscillator). The oscillator generates an internal clock signal of an oscillation frequency corresponding to the oscillation control signal, and supplies the internal clock signal to a frequency divider. The frequency divider generates a comparison clock signal by frequency-dividing the internal clock signal generated by the oscillator by a predetermined frequency dividing ratio, and supplies the comparison clock signal to the phase and frequency comparator.
Japanese Patent Laid-Open No. 2006-180349 (hereinafter referred to as Patent Document 1) proposes a mechanism that enables a state of operation of a phase-locked loop circuit to be determined accurately on the basis of an output signal of a phase and frequency comparator.
In the mechanism described in Patent Document 1, an operation state determining section determines whether a PLL frequency synthesizer is in a desired operation state on the basis of whether a control voltage output from a loop filter is within a predetermined voltage range. A current control circuit generates a frequency division control signal for controlling a frequency divider on the basis of a determination signal from the operation state determining section. At this time, the current control circuit generates the frequency division control signal so as to reduce the driving current of the frequency divider within a range where the PLL frequency synthesizer maintains the desired operation state.
With such a mechanism, the state of operation of the PLL frequency synthesizer can be determined accurately, and the erroneous operation of the feedback frequency dividing circuit can be detected. Further, the power consumption of the frequency divider and the PLL frequency synthesizer can be reduced by providing the current control circuit.